
//refer to Figure 4.17(P.257)

module riscv_pc(
	input rst,
	input clk,
	input [31:0] pc_i,
	output [31:0] pc_o);

reg [31:0] pc_q;
reg [1:0] rst_cnt;
reg last_rst;

always @(negedge clk or negedge rst) begin 
    if (!rst) begin
        rst_cnt <= 1;
        last_rst <= 1;
    end
    else if (last_rst==1) begin
        if (rst_cnt == 0)
            last_rst <= 0;
        else
            rst_cnt <= rst_cnt + 1;
    end
end

always @(negedge clk) begin 
    if (last_rst==1)
        pc_q <= 32'h0000_0000;
    else
		pc_q <= pc_i;
end

assign pc_o = pc_q;

endmodule

